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? semiconductor components industries, llc, 2006 august, 2006 ? rev. 0 1 publication order number: ncp5612/d ncp5612 high efficiency ultra small thinnest white led driver the ncp5612 product is a dual output led driver dedicated to the lcd display backlighting. the built?in dc/dc converter is based on a high efficient charge pump structure with operating mode 1x and 1.5x. it provides a peak 87% efficiency together with a 0.2% led to led matching. features ? support the single wire serial link protocol ? peak efficiency 90% with 1x and 1.5x mode ? programmable dimming icon function ? built?in short circuit protection ? provides 16 steps current control ? controlled start?up inrush current ? built?in automatic open load protection ? tight 0.2% matching tolerance ? accurate 1% output current tolerance ? smallest available package on the market ? this is a pb?free device typical applications ? portable back light ? digital cellular phone camera photo flash ? lcd and key board simultaneous drive figure 1. typical single wire white led driver c2 c1 220 nf/10 v c3 c4 gnd d2 lwy87s d1 lwy87s r1 10k mcu i/o pin c5 gnd gnd gnd 1 led1 2 led/icon 3 4 cntl 5 nc 6 7 c2p 8 c2n 9 c1p 10 11 c1n 12 u1 ncp5612 v cc v bat 1 f/6.3 v 1 f/6.3 v v cc?cpu 220 nf/10 v 1 f/10 v v bat i ref v out gnd llga12 (2x2 mm) mu suffix case 513aa pin connections http://onsemi.com marking diagram 1 nc c1p 1 v bat i ref led2 c2n 3 4 5 10 9 8 7 yd m yd = specific device code m = date code = pb?free package (note: microdot may be in either location) 2 12 11 6 led1 cntl c2p v out (top view) device package shipping ? ordering information NCP5612MUTBG llga12 (pb?free) 3000/t ape & ree l ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. gnd c1n
ncp5612 http://onsemi.com 2 1 f/6.3 v c3 v bat 11 charge pump dc/dc converter 12 10 c1 9 8 c2 7 v out lwy87s d1 d2 gnd 1 f/10 v c4 2 3 q1 q2 overvoltage current mirrors v bat digital control 6 nc analog control 4 10 k r1 1 overtemperature figure 2. simplified block diagram 220 nf 220 nf 5 cntl v bat lwy87s gnd gnd gnd gnd gnd 150 k
ncp5612 http://onsemi.com 3 pin function description pin no. symbol function description 1 gnd power this pin is the ground signal for the power analog blocks and must be connected to the system ground. this pin is the ground reference for the dc/dc converter and the output current control. the pin must be connected to the system ground, a ground plane being strongly recommended. 2 led1 input, power this pin sinks to ground and monitors the current flowing into the first led, intended to be used in backlight application. the current is limited to 30 ma maximum (note 2). the led1 is deactivated when the icon bit of the led?reg register is high. the led1 is automatically disconnected when an open load is sensed pin 2 during the operation. 3 led2 input, power this pin sinks to ground and monitors the current flowing into the second led, intended to be used in backlight application. the current is limited to 30 ma maximum (note 2). the led2 fulfills the icon function, led1 being deactivated, when the icon bit of the led?reg register is high. the led2 is automatically disconnected when an open load is sensed pin 3 during the operation. 4 i ref input, analog this pin provides the reference current, based on the internal band?gap voltage reference, to control the output current flowing in the led. a 1% tolerance, or better, resistor shall be used to get the highest accuracy of the led biases. an external current source can be used to bias this pin to dim the light coming out of the led. in no case shall the voltage at pin 4 be forced either higher or lower than the 600 mv provided by the internal reference. 5 cntl input, digital this pin supports the flow of data between the external mcu and the ncp5612 internal registers. the protocol makes profit of a single wire structure associated to a serial 8 bits format data flow. 6 nc ? no internal connection 7 v out output, power this pin provides the output voltage supplied by the dc/dc converter. the v out pin must be decoupled to ground by a 1 f ceramic capacitor located as close as possible to the pin. cares must be observed to minimize the parasitic inductance at this pin. the circuit shall not operate without such bypass capacitor connected across the v out pin and ground. the output voltage is internally clamped to 5.5 v maximum in the event of no load situation. on the other hand, the output current is limited to 40 ma (typical) in the event of a short circuit to ground. 8 c2p power one side of the external charge pump capacitor (c fly ) is connected to this pin, associated with c2n (note 1) 9 c2n power one side of the external charge pump capacitor (c fly ) is connected to this pin, associated with c2p (note 1) 10 c1p power one side of the external charge pump capacitor (c fly ) is connected to this pin, associated with c1n (note 1) 11 v bat input, power input battery voltage to supply the analog and digital blocks. the pin must be decoupled to ground by a 1.0 f minimum ceramic capacitor. 12 c1n power one side of the external charge pump capacitor (c fly ) is connected to this pin, associated with c1p (note 1) 1. using low esr ceramic capacitor, 50 m maximum, is mandatory to optimize the charge pump ef ficiency. 2. total dc/dc output current is limited to 60 ma.
ncp5612 http://onsemi.com 4 maximum ratings rating symbol value unit power supply v bat 7.0 v output power supply vout 7.0 v digital input v oltage digital input current cntl ?0.3 < v < v bat 1.0 v ma human body model: r = 1500 , c = 100 pf (note 3) machine model esd 2.0 200 kv v llga12 package power dissipation @ t a = +85 c (note 4) thermal resistance, junction?to?case thermal resistance, junction?to?air p d r jc r ja 200 51 200 mw c/w c/w operating ambient temperature range t a ?40 to +85 c operating junction temperature range t j ?40 to +125 c maximum junction t emperature t jmax +150 c storage temperature range t stg ?65 to +150 c latch?up current maximum rating per jedec standard: jesd78 ? 100 ma moisture sensitivity (note 5) ? 1 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 3. this device series contains esd protection and exceeds the following tests: human body model (hbm) 2.0 kv per jedec standard: jesd22?a114. machine model (mm) 200 v per jedec standard: jesd22?a115. 4. the maximum package power dissipation limit must not be exceeded. 5. moisture sensitivity level (msl): 1 per ipc/jedec standard: j?std?020a. power supply section (typical values are referenced to t a = +25 c, min & max values are referenced ?40 c to +85 c ambient temperature, operating conditions 2.85 v < v bat < 5.5 v, unless otherwise noted.) rating pin symbol min typ max unit power supply 11 v bat 2.7 ? 5.5 v continuous dc current in the load @ v f = 3.8 v, 3.2 v < v bat < 5.5 v, icon = l (30 ma per led) 7 i out 60 ? ? ma output icon current (icon bit = h) @ 3.2 v < v bat < 4.2 v, t a = +25 c 7 i icontol ? 450 550 a continuous output short circuit current 7 i sch ? 40 100 ma output voltage compliance (ovp) 7 v out 4.8 ? 5.7 v dc/dc start time (c out = 1.0 f) from end of the cntl t dst delay to full load operation, @ v bat = 3.6 v 12 t start ? 150 ? s output voltage t urn?off (c out = 1 f) from last low level at cntl pin to v out = 5% 12 t off ? 500 ? s standby current, 0 c < t a < +85 c v bat = 3.6 v, i out = 0 ma, icon = l 11 i stdb ? ? 1.0 a operating current, @ i out = 0 ma, icon = h, v bat = 3.6 v 11 i op ? 600 ? a output led to led current matching, v bat = 3.6 v, i led = 10 ma, led1 & led2 are identical ?25 c < t a < 85 c 2, 3 i mat ? 0.2 1.0 % output current tolerance @ v bat = 3.6 v, i led = 10 ma ?25 c < ta < 85 c 2, 3 i tol ? 1.0 ? % charge pump operating frequency ? f pwr ? 1.0 ? mhz thermal shutdown protection ? t sd ? 160 ? c thermal shutdown protection hysteresis ? t sdh ? 30 ? c efficiency ? led1 = led2 = 10 ma, v f = 3.2 v, v bat = 3.8 v (total = 20 ma) efficiency ? led1 = led2 = 30 ma, v f = 3.75 v, v bat = 3.8 v (total = 60 ma) ? ? e pwr ? ? 87 84 ? ? %
ncp5612 http://onsemi.com 5 analog section (typical values are referenced to t a = +25 c, min & max values are referenced ?40 c to +85 c ambient temperature, operating conditions 2.85 v < v bat < 5.5 v, unless otherwise noted.) rating pin symbol min typ max unit reference current @ v ref = 600 mv (note 7) 4 i ref 1.0 ? 60 a reference voltage (note 7) 0 c < t a < +85 c 4 v ref ?3% 600 +3% mv base reference current (i ref ) current ratio ? i ledr ? 500 ? ? 6. the overall output current tolerance depends upon the accuracy of the external resistor. using 1% or better resistor is recom mended. 7. the external circuit must not force the i ref pin voltage either higher or lower than the 600 mv specified. digital parameters section (typical values are referenced to t a = +25 c, min & max values are referenced ?40 c to +85 c ambient temperature, operating conditions 2.85 v < v bat < 5.5 v, unless otherwise noted.) note: digital inputs undershoot < ? 0.30 v to ground, digital inputs overshoot < 0.30 v to v bat . rating pin symbol min typ max unit positive going input high voltage threshold, cntl signals 5 v ih 1.4 ? v bat v negative going input low voltage threshold, cntl signals 5 v il ? ? 0.6 v pull down resistor 5 r cntl ? 150 ? k delay between two consecutive frame (note 9) 5 t idle 10 ? ? s wake up delay (note 9) 5 t wkp ? ? 1.0 s cntl signal rise and fall time (note 9) 5 t r , t f ? ? 200 ns clocked cntl high (note 9) 5 t on ? ? 75 s cntl low (note 9) 5 t on , t off 1.0 ? ? s cntl store data delay (note 9) 5 t dst ? 200 300 s input cntl frequency (note 9) 5 f cntl ? ? 400 khz 8. see timings reference 9. parameter not tested in production, guaranteed by design.
ncp5612 http://onsemi.com 6 application information figure 3. timings reference 90% 10% 90% bit = 1 bit = 0 bit = 0 v ih v il t wkp t on t off t f t r figure 4. basic cellular phone chip set digital output levels ground 100 mv/step 1400 mv 600 mv v oh @ v ccio = 3.0 v 2600 mv v oh @ v ccio = 2.6 v 2400 mv v ihsw v il v ol @ motorola: 500 mv v ol @ qualcomm: 450 mv v ol @ intel: 400 mv dc/dc operation the converter is based on a charge pump technique to generate a dc voltage capable to supply the white led load. the system regulates the current flowing into each led by means of internal current mirrors associated with the white diodes. consequently, the output voltage will be equal to the v f of the led, plus the drop voltage (ranging from 150 mv to 400 mv, depending upon the output current and v bat / v f ratio) developed across the internal nmos mirror. typically, assuming a standard white led forward biased at 10 ma, the output voltage will be 3.6 v. the built?in ovp circuit continuously monitors the output voltage and stops the converter when the voltage is above 5.0 v typical. the converter resumes to normal operation when the voltage drops below the typical 5.0 v (no latch?up mechanism). consequently, the chip can operate with no load during any test procedures. load current calculation the load current is derived from the 600 mv reference voltage provided by the internal band gap associated to the external resistor connected across i ref pin and ground (see figure 5). in any case, no voltage shall be forced at i ref pin, either downward or upward. the reference current is multiplied by the internal current mirror, associated to the number of pulses as depicted figure 9, to yield the output load current. since the reference voltage is based on a temperature compensated band gap, a tight tolerance resistor will provide a very accurate load current. the resistor is calculated from the ohm?s law (r bias = v ref /i ref ) and define the maximum current flowing into the led when 20 pulses have been counted at the cntl pin. since the reference current must be between the minimum and maximum specified, the resistor value will range between r bias = 300/30 ma = 10 k and r bias = 300/0.5 ma = 600 k . obviously, the tolerance of such a resistor must be 1% or better, with a 100 ppm thermal coefficient, to get the expected overall tolerance. typical applications will run with r bias = 10 k to make profit of the full dynamic range provided by the s?wire data byte.
ncp5612 http://onsemi.com 7 figure 5. basic reference current source 600 mv pin 4 vbandgap r1 gnd gnd pin 2 & 3 led return note: the i ref pin must never be biased by an external voltage. i ref load connection the ncp5612 is capable to drive the two led simultaneously, as depicted (see figure 1), but the load can be arranged to accommodate one or two led if necessary in the application (see figure 6). in this case, the two current mirrors can be connected in parallel to drive a single powerful led, thus yielding 60 ma current capability in a single led. c4 gnd 7 ncp5612 d2 lwy87s d1 lwy87s 2 3 figure 6. typical single and double led connections 1 f/6.3 v c4 gnd 7 ncp5612 d1 lwy87s 2 3 1 f/6.3 v finally, an external network can be connected across v out and ground, but the current through such network will not be regulated by the ncp5612 chip (see figure 7). on top of that, the total current out of the v out pin shall be limited to 60 ma. c4 1uf/6.3v gnd 7 2 3 ncp5612 d3 lwy87s d4 lwy87s r1 220r r2 220r gnd 5ma 5ma figure 7. extra load connected to v out d1 lwy87s d2 lwy87s 20 ma 20 ma single wire serial link protocol the proposed s?wire uses a pulse count technique already existing in the data exchange systems. the protocol supports broken transmission, assuming the hold time is shorter than the maximum 200 s typical specified in the data sheet. the s?wire details are provided in the and8264 application note. based on the two examples provided in figure 8, the cntl pin supports two digital level: cntl = low the system is shut?off and no current flow in either led1 or led2. cntl = high the system is active and the two led are powered according to the selected sequence. there is no time delay associated with the low state and the led are switched off when the cntl signal drops to low. to program a new led configuration, one shall send the number of pulses on the cntl pin according to the true table: ? the internal counter is reset to zero on the first negative going transient present on the cntl pin
ncp5612 http://onsemi.com 8 ? the first four positive going pulses are used to control the icon (led2): 1. pulse #1 icon = 100 a 2. pulse #2 icon = 150 a 3. pulse #3 icon = 250 a 4. pulse #4 icon = 450 a ? the fifth positive pulse will clear the icon and activate the normal operation of led1 and led2 ? the pulses from the fifth to the twentieth will increase the led current according to a pseudo logarithmic scale (see figure 9). ? any pulses beyond the twentieth will not make change to the led current if the delay between the pulses is shorter than 75 s. ? the system returns to zero if a pulse, delayed by 200 s ? t dst ? , follows the twentieth one and the cycle restart from the beginning. once the expected led current value is reached, the cntl pin must stay high to store the new data and maintain the led active. the contain of the counter is stored into the internal led registers at the end of the built?in 200 s typical delay: no action will take place during the end of the last positive going pulse and the end of the t dst delay. such a protocol prevent the system for broken transmission. on the other hand, in order to avoid corrupted data transmission, the high level shall be 75 s maximum during a given data frame. consequently, the pulse frequency is bounded by a 13 khz minimum and a 400 khz maximum. figure 8. basic ncp5612 programming sequence example #1: cntl led1= 0 ma example #2: cntl 1 23 start bit negative going edge shut down mode clear counter led1=led0= 0 ma led2 = icon led1= 6 ma led2 = 6 ma led1=led2 = 6 ma pulse count pulse count example #3: cntl 1234 5 6789 led1= 30 ma led2 = 30 ma 10 icon = disabled led1=led2 = 30 ma pulse count 11 12 13 14 15 16 17 18 19 20 led1=led2 = 0 ma note: timings are not scaled. t dst 1234 5 678910 t dst icon = disabled t eh icon = 250 a t eh max 75 s when clocked t dst t el
ncp5612 http://onsemi.com 9 dimming the built?in single wire serial link interface provides a simple way to accurately control the output current flowing in the two led. provision have been made, at silicon level, to provide a full dimming of the backlight (normal mode of operation), the icon current being adjustable in four steps when it is activated. table 1. led dimming configuration pulse count led activity pulse 1 led#2 = 100 a, led#1 de?activated pulse 2 led#2 = 150 a, led#1 de?activated pulse 3 led#2 = 250 a, led#1 de?activated pulse 4 led#2 = 450 a, led#1 de?activated pulse 5 to pulse 20 icon de?activated, normal back- light takes place the dc/dc converter is switched off and the two led are disconnected when led?reg=$00. when the icon mode is activated, the dc/dc converter is switched off, led#1 is deactivated from the led current sense and the programmed bias current (powered from the v bat source) is forced into led#2. bit clock i?led(ma) bit clock i?led(ma) 1 1 9 12 2 2 10 14 3 3 11 16 4 4 12 19 5 5 13 22 6 6 14 25 7 8 15 28 8 10 16 31 figure 9. typical output current slope i out (ma) 2 0 15 10 5.0 0 35 30 25 20 15 10 5.0 0 i out = f(bit clock) (linear scale) bit clock figure 10. typical efficiency
ncp5612 http://onsemi.com 10 figure 11. typical led to led current matching c3 c2 220 nf/6.3 v c4 c1 gnd gnd d1 lwy87s d2 lwy87s r1 10 k led1 led2 data irefbk z1 gnd 1 2 3 4 5 6 7 8 9 10 j2 s?wire port gnd tp1 data gnd 1 2 j1 power gnd gnd 1 led1 2 led/icon 3 4 cntl 5 nc 6 7 c2p 8 c2n 9 c1p 10 11 c1n 12 u1 ncp5612 figure 12. demo board schematic diagram 4.7 f/10 v v bat 220 nf/6.3 v tp2 v out 1.0 f/10 v i ref v bat v out v out
ncp5612 http://onsemi.com 11 package dimensions llga12 mu suffix case 513aa?01 issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994 . 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.20 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. ???? ???? ???? a d e b c 0.10 pin one 2 x reference 2 x top view side view bottom view a l d2 e2 c c 0.10 c 0.10 c 0.08 12x a1 seating plane e/2 e 11x k note 3 b 12x 0.10 c 0.05 c a b b dim min max millimeters a 0.50 0.60 a1 0.00 0.05 b 0.15 0.25 d 2.00 bsc d2 0.80 1.00 e 2.00 bsc e2 0.55 0.65 e 0.40 bsc k 0.25 ??? l 0.30 0.50 2 6 11 7 l1 0.40 0.60 1 12 l1 9x *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint* dimensions: millimeters 12x 0.23 2.30 0.40 pitch 0.93 0.63 0.56 11x 0.66 0.91 1 2.06 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 ncp5612/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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